IDT82V2058 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT82V2058 Datasheet PDF : 52 Pages
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IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
Pin No.
QFP144 BGA160
Description
OE
I
114 E14 OE: Output Driver Enable
Pulling this pin to low can make all driver output into high impedance state immediately for redundancy
application without external mechanical relays. In this condition, all the other internal circuits remain
active.
CLKE I
115 E13 CLKE: Clock Edge Select
The signal on this pin determins the active edge of RCLKn and SCLK in clock recovery mode, or
determines the active level of RDPn and RDNn in the data recovery mode. (Refer to Functional
Description and Table-2).
JTAG Signals
TRST
I
95
Pull up
G12 TRST: JTAG Test Port Reset (Active Low)
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pullup resistor
and it can be left disconnected.
TMS
I
96
F11 TMS: JTAG Test Mode Select
Pull up
The signal on this pin controls the JTAG test performance and is clocked into the device on rising edges
of TCK. This pin has an internal pullup resistor and it can be left disconnected.
TCK
I
97
F14 TCK: JTAG Test Clock
This pin input the clock of the JTAG Test. The data on TDI and TMS are clocked into the device on rising
edges of TCK, while the data on TDO is clocked out of the device on falling edges of TCK.
TDO O
98
F13 TDO: JTAG Test Data Output
Tri-state
This pin output the serial data of the JTAG Test. The data on TDO is clocked out of the device on falling
edges of TCK. TDO is a Tri-state output signal. It is active only when scanning of data is out.
TDI
I
99
F12 TDI: JTAG Test Data Input
Pull up
This pin input the serial data of the JTAG Test. The data on TDI is clocked into the device on rising edges
of TCK. This pin has an internal pullup resistor and it can be left disconnected.
IC
-
93
G13 IC: Internal Connected
(Leave it open for normal operation.)
IC
-
94
H13 IC: Internal Connected
(Leave it open for normal operation.)
Supplies and Grounds
VDDIO -
17
G1 3.3V I/O Power Supply
92
G14
GNDIO -
18
G4 I/O GND
91
G11
VDDT0 -
44 N4,P4 3.3V / 5V Power Supply for Transmitter Driver
VDDT1
53 L4,M4 All VDDT pins must be connected to either 3.3V or 5V. It is not allowed to leave any of the VDDT pins
VDDT2
56 L11,M11 open (not-connected) even if the channel is not used.
VDDT3
65 N11,P11
VDDT4
116 A11,B11
VDDT5
125 C11,D11
VDDT6
128 C4,D4
VDDT7
137 A4,B4
GNDT0 -
47 N6,P6 Analog GND for Transmitter Driver
GNDT1
50 L6,M6
GNDT2
59 L9,M9
GNDT3
62 N9,P9
GNDT4
119 A9,B9
GNDT5
122 C9,D9
GNDT6
131 C6,D6
GNDT7
134 A6,B6
VDDD -
19
H1 3.3V Digital / Analog Core Power Supply
VDDA
90
H14
GNDD -
20
H4 Digital / Analog Core GND
GNDA
89
H11
10
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