IDT821054 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT821054

QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

Integrated Device Technology 

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

INDUSTRIAL TEMPERATURE RANGE

Name

CS

CI

CO

CCLK

MCLK

RESET

INT12

INT34

CHCLK1

CHCLK2

Type Pin Number

Description

I

17

Chip Selection.

A logic low level on this pin enables the Serial Control Interface.

I

19

Serial Control Interface Data Input.

Control data input pin. CCLK determines the data rate.

O

20

Serial Control Interface Data Output (Tri-State).

Control data output pin. CCLK determines the data rate.

I

18

Serial Control Interface Clock.

This is the clock for the Serial Control Interface. It can be up to 8.192 MHz.

Master Clock Input.

I

22 This pin provides the clock for the DSP of the IDT821054. The frequency of the MCLK can be 1.536 MHz,

1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz.

I

23

Reset Input.

Forces the device to default mode. Active low.

Interrupt Output Pin for Channel 1-2.

O

34 Active high interrupt signal for Channel 1 and 2, open-drain. It reflects the changes on the corresponding

SLIC input pins.

Interrupt Output Pin for Channel 3-4.

O

15 Active high interrupt signal for Channel 3 and 4, open-drain. It reflects the changes on the corresponding

SLIC input pins.

O

33

Chopper Clock Output One.

Provides a programmable output signal (2 -28 ms) synchronous to MCLK.

O

16

Chopper Clock Output Two.

Provides a programmable output signal (256 kHz, 512 kHz or 16.384 MHz) synchronous to MCLK.

8

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