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IDT7M1001S40C

128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

Integrated Device Technology 

IDT7M1001/1003

128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)(1,2,4)

ADDRESS

t RC

t AA

t OH

DATA OUT

PREVIOUS DATA VALID

t OH

DATA VALID

2804 drw 06

TIMING WAVEFORM OF READ CYCLE NO. 2 (EITHER SIDE)(1,3,5)

t ACS

CS

t OE

OE

DATA OUT

ICC

CURRENT

ISB

t OLZ (6)

t PU (6)

tCLZ (6)

50%

NOTES:

1. R/W is HIGH for Read Cycles

2. Device is continuously enabled. CS = LOW. This waveform cannot be used for semaphore reads.

3. Addresses valid prior to or coincident with CS transition LOW.

4. OE = LOW.

5. To access RAM, CS = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.

6. This parameter is guaranteed by design but not tested.

t CHZ (6)

t OHZ(6)

DATA VALID

t

(6)

PD

50%

2804 drw 07

7.5

6

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