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IDT74FST16163232PF Просмотр технического описания (PDF) - Integrated Device Technology

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IDT74FST16163232PF
IDT
Integrated Device Technology IDT
IDT74FST16163232PF Datasheet PDF : 6 Pages
1 2 3 4 5 6
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
ICC
Quiescent Power Supply Current VCC = Max.
TTL Inputs HIGH
VIN = 3.4V(3)
— 0.5 1.5
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
30
40
Enable Pin Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN = VCC
— 4.8 6.4
Outputs Open
VIN = GND
CLK Pin Toggling
(16 Switches Toggling) VIN = 3.4
— 5.1 7.2
fi = 10MHz
VIN = GND
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fiN)
ICC = Quiescent Current
ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fi = Input Frequency
N = Number of Switches Toggling at fi
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Unit
mA
µA/
MHz/
Switch
mA
3511 tbl 06
Symbol
Description
Condition(1)
Min.(2)
Typ.
Max.
Unit
tPLH Data Propagation Delay
tPHL
A to B, B to A(3,4)
CL = 50pF
RL = 500
0.25
ns
tCEWS Clock Enable Set-Up Time
CLKEN to CLK Low-to-High
ns
tCENH Clock Enable Hold Time
CLKEN to CLK Low-to-High
ns
tBX
Switch Multiplex Delay
CLK to A, B
1.5
6.5
ns
tPZH Switch Turn on Delay
tPZL
CLK to A, B
1.5
6.5
ns
tPHZ Switch Turn off Delay
1.5
7
ns
tPLZ
|QCI|
CLK to A, B
Charge Injection, Typical(5,7)
1.5
pC
|QDCI| Differential Charge Injection, Typical(6,7)
0.5
NOTES:
3511 tbl 07
1. See test circuit and waveforms.
2. Minimum limits guaranteed but not tested.
3. This parameter is guaranteed by design but not tested.
4. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant
for the switch alone is of the order of 2.5ns for 50pF load. Since this time is constant and much smaller than the rise/fall times of typical driving signals,
it adds very little propagation delay to the system. Propagation delay on the bus switch when used in a system is determined by the driving circuit on the
driving side of the switch and its interaction with the load on the driven side.
5. Measured at switch turn off, load = 50 pF in parallel with 10 Mscope probe, VIN = 0.0 volts.
6. Measured at switch turn off through bus multiplexer, (e.g.- A to B1 = >A to B2), load = 50 pF in parallel with 10 Mscope probe, VIN at A = 0.0 volts. Charge
injection is reduced because the injection from the turn off of the A to B1 switch is compensated by the turn on of the A to B2 switch.
7. Characterized parameter. Not 100% tested.
4

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