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IDT74FST163211PA

24-BIT BUS SWITCH

Integrated Device Technology 

IDT74FST163211

24-BIT BUS SWITCH

INDUSTRIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

V CC

7.0V

SAME PHASE

INPUT TRANSITION

500Ω

tPLH

tPHL

VIN

Pulse

Generator

VOUT

D.U.T.

50pF

500Ω

RT

CL

OUTPUT

tPLH

tPHL

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V

0V

VOH

1.5V

VOL

3V

1.5V

0V

Propagation Delay

Test Circuits for All Outputs

SWITCH POSITION

Test

Open Drain

Disable Low

Enable Low

All Other Tests

Switch

Closed

Open

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

VCC

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS

CONTROL

tSU

tH

tREM

SYNCHRONOUS

CONTROL

tSU

tH

Set-up, Hold, and Release Times

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

1 MHz

Signal

Generator

Enable/Select(1)

Switch In

Switch In

(MUX) (2)

Switch

D.U.T. Out

VOUT (3)

CL =

50pF

Charge Injection

NOTES:

1. Select is used with multiplexers for measuring IQDCII during multiplexer select. During

all other tests Enable is used.

2. Used with multiplexers to measure IQDCII only.

3. Charge Injection = ∆VOUT CL, with Enable toggling for IQCII or Select toggling for IQDCII.

∆VOUT is the change in VOUT and is measured with a 10MΩ probe.

LOW-HIGH-LOW

PULSE

1.5V

ENABLE

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

tPZL

SWITCH

CLOSED

tPZH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

DISABLE

tPLZ

3.5V

1.5V

0.3V

tPHZ

1.5V

0V

0.3V

3V

1.5V

0V

3.5V

VOL

VOH

0V

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

tW

HIGH-LOW-HIGH

PULSE

1.5V

Pulse Width

5

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