IDT74ALVCH162721PF Просмотр технического описания (PDF) - Integrated Device Technology
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IDT74ALVCH162721PF
Integrated Device Technology
IDT74ALVCH162721PF Datasheet PDF : 6 Pages
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IDT74ALVCH162721
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD
6
VIH
2.7
VT
1.5
6
2 x Vcc
V
SAME PHASE
2.7
Vcc
V
INPUT TRANSITION
tPLH
tPHL
1.5
Vcc / 2
V
OUTPUT
VLZ
300
300
150
mV
VHZ
300
300
150
mV
tPLH
tPHL
CL
50
50
30
pF
OPPOSITE PHASE
NEW16link
INPUT TRANSITION
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
TEST CIRCUITS FOR ALL OUTPUTS
VCC
VLOAD
Open
Pulse(1, 2)
V IN
Generator
VOUT
D.U.T.
500Ω
GND
RT
500Ω
CL
DEFINITIONS:
ALVC Link
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
OUTPUT SKEW - TSK (x)
Switch
VLOAD
GND
Open
INPUT
tPLH1
tPHL1
OUTPUT 1
tSK (x)
tSK (x)
OUTPUT 2
tPLH2
tPHL2
NEW16link
V IH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
ALVC Link
ENABLE AND DISABLE TIMES
CONTROL
INPUT
ENABLE
tPZL
DISABLE
VIH
VT
0V
tPLZ
OUTPUT
SW ITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT
NORMALLY
SW ITCH
OPEN
HIGH
V L O A D /2
VT
tPHZ
VT
0V
V L O A D /2
VLZ
VOL
VOH
VHZ
0V
NOTE:
ALVC Link
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
V IH
DATA
VT
INPUT
tSU
tH
0V
TIMING
V IH
INPUT
VT
0V
ASYNCHRONOUS
CONTROL
tREM
V IH
VT
0V
SYNCHRONOUS
V IH
VT
CONTROL
tSU
tH
0V
ALVC Link
PULSE WIDTH
L O W -H IG H -LO W
PULSE
H IG H -L O W -H IG H
PULSE
VT
tW
VT
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPH L2 - tPHL1
NOTES:
ALVC Link
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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