![](/html/Supertex/41448/page3.png)
Truth Table
HVEN
H
POL
H
H
L
L
H
L
L
HVOUT1
HVIN
GND
LVIN
GND
Timing Diagram
POL
50%
HVOUT2
GND
HVIN
GND
LVIN
50%
HVOUT1
GND
80%
t(ON)
5%
t(OFF)
Figure 1
HVEN
50%
HVOUT1
LVIN
Block Diagram
LVIN
HVIN
VDD
80%
tEN(ON)
Figure 2
Level
Translator
Level
Translator
HVEN
POL
GND
CMOS
Logic
Level
Translator
Level
Translator
HV508
VIH
VIL
VIN
or LVIN
VIH
VIL
HVIN
HVOUT1
HVOUT2
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3
12/13/010
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