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IDT72V83

3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO

Integrated Device Technology 

IDT72V81/72V82/72V83/72V84/72V85

tRSC

RS

tRS

tRSS

W

tRSS

R

tEFL

EF

tHFH, tFFH

HF, FF

NOTES:

1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

Figure 2. Reset

Commercial Temperature Range

tRSR

3966 drw 04

R

Q0-Q8

W

D0-D8

tRC

tA

tRR

tRPW

tA

tRLZ

tWPW

tDV

DATA OUT VALID

tWC

tWR

tRHZ

DATA OUT VALID

tDS

tDH

DATA IN VALID

DATA IN VALID

Figure 3. Asynchronous Write and Read Operation

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LAST WRITE

IGNORED

WRITE

FIRST READ

ADDITIONAL FIRST

READS

WRITE

R

W

tWFF

FF

tRFF

Figure 4. Full Flag From Last Write to First Read

5

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