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IDT72V81
(Rev.:2006)

3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO

Integrated Device Technology 

IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO

512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9

COMMERCIAL TEMPERATURE RANGE

TABLE I—RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Mode

Reset

Retransmit

Read/Write

Inputs

Internal Status

RS

RT

XI

Read Pointer

Write Pointer

0

X

0

Location Zero

Location Zero

1

0

0

Location Zero

Unchanged

1

1

0

Increment(1)

Increment(1)

NOTE:

1. Pointer will increment if flag is High.

Outputs

EF

FF

HF

0

1

1

X

X

X

X

X

X

TABLE II—RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Mode

Reset First Device

Reset All Other Devices

Read/Write

Inputs

Internal Status

RS

FL

XI

Read Pointer

Write Pointer

0

0

(1)

Location Zero

Location Zero

0

1

(1)

Location Zero

Location Zero

1

X

(1)

X

X

Outputs

EF

FF

0

1

0

1

X

X

NOTE:

1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,

sion Input, HF = Half-Full Flag Output

XI = Expan-

XOA

W

D

9

FFA

EFA

FIFO A

FLA

XIA

72V81/72V82

72V83/72V84

72V85

XOB

FFB

EFB

FIFO B

9

9

FLB

XIB

XOA

R

Q

V CC

FULL

RSA

FFA

EFA

9

FIFO A

FLA

XIA

72V81/72V82

72V83/72V84

72V85

XOB

FFB

9

EFB

FIFO B

FLB

EMPTY

XIB

3966 drw 16

Figure 14. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 and 32,768 x 9 FIFO Memory (Depth Expansion)

9

JULY 17, 2006

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