IDT72V36106 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72V36106

3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFOTM

WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)

Symbol

Parameter

IDT72V3686L10

IDT72V3696L10

IDT72V36106L10

IDT72V3686L15

IDT72V3696L15

IDT72V36106L15

Min.

Max.

Min.

Max.

Unit

fS

Clock Frequency, CLKA, CLKB, or CLKC

—

100

—

66.7

MHz

tCLK

Clock Cycle Time, CLKA, CLKB, or CLKC

10

—

15

—

ns

tCLKH

Pulse Duration, CLKA, CLKB, or CLKC HIGH

4.5

—

6

—

ns

tCLKL

Pulse Duration, CLKA, CLKB, OR CLKC LOW

4.5

—

6

—

ns

tDS

Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑

3

tENS1

Setup Time, CSA and W/RA before CLKA↑; CSB

4

before CLKB↑

—

4

—

4.5

—

ns

—

ns

tENS2

tRSTS

tFSS

Setup Time, ENA, and MBA before CLKA↑; RENB

and MBB before CLKB↑; WENC and MBC before CLKC↑

Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2

LOW before CLKA↑ or CLKB↑(1)

Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH

3

—

4.5

—

ns

5

—

5

—

ns

7.5

—

8.5

—

ns

tBES

Setup Time, BE/FWFT before MRS1 and MRS2 HIGH

7.5

—

7.5

—

ns

tSDS

tSENS

tFWS

tRTMS

Setup Time, FS0/SD before CLKA↑

Setup Time, FS1/SEN before CLKA↑

Setup Time, BE/FWFT before CLKA↑

Setup Time, RTM before RT1; RTM before RT2

3

—

4

—

ns

3

—

4

—

ns

0

—

0

—

ns

5

—

5

—

ns

tDH

tENH

tRSTH

tFSH

Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB,

RENB, and MBB after CLKB↑; WENC and MBC after CLKC↑

Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2

LOW after CLKA↑ or CLKB↑ (1)

Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH

0.5

—

1

0.5

—

1

4

—

4

2

—

2

—

ns

—

ns

—

ns

—

ns

tBEH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

2

—

2

—

ns

tSDH

tSENH

tSPH

tRTMH

tSKEW1(2)

Hold Time, FS0/SD after CLKA↑

Hold Time, FS1/SEN HIGH after CLKA↑

Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH

Hold Time, RTM after RT1; RTM after RT2

Skew Time, between CLKA↑ and CLKB↑ for EFB/ORB and

FFA/IRA; between CLKA↑ and CLKC↑ for EFA/ORA and

FFC/IRC

0.5

—

1

—

ns

0.5

—

1

—

ns

2

—

2

—

ns

5

—

5

—

ns

5

—

7.5

—

ns

tSKEW2(2,3) Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA;

between CLKA↑ and CLKC↑ for AEA and AFC

12

—

12

—

ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.

3. Design simulated, not tested.

9

Share Link: