IDT72V3612L15PQF Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3612L15PQF Datasheet PDF : 25 Pages
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IDT72V3612 3.3V, CMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3612 with CLKA and CLKB set to
fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3612 may be calculated by:
where:
PT = VCC x ICC(f) + Σ(CL x (VOH - VOL)2 x fO)
N
N=
number of outputs = 36
CL =
output capacitance load
fo =
switching frequency of an output
VOH =
output HIGH level voltage
VOL =
output LOW level voltage
When no reads or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated
by:
PT = VCC x fS x 0.025 mA/MHz
175
150
125
100
75
50
25
0
0
fdata = 1/2 fS
TA = 25°C
CL = 0 pF
VCC = 3.3V
VCC = 3.6V
VCC = 3.0V
10
20
30
40
50
60
70
fS Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
80
90
4663 drw 04
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