IDT72V3640L10BBI Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3640L10BBI Datasheet PDF : 46 Pages
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IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the OE input used
to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
PIN CONFIGURATIONS (CONTINUED)
A1 BALL PAD CORNER
A
ASYW
B
SEN
C
D35
D
D32
E
D29
WEN
IW
D34
D31
D28
WCLK PAF FF/IR
PRS
LD
MRS
D33 FWFT/SI OW
D30
VCC
VCC
D27
VCC
GND
F
D26 D25 D24
VCC
GND
G
D21
D22 D23
VCC
GND
H
D18 D19 D20
VCC
GND
J
D15 D16 D17
VCC
VCC
K
D12 D13 D14
D3
D0
L
D10 D11
D6
D4
D1
M
D9
D8
D7
D5
D2
HF
FS0
VCC
GND
GND
GND
GND
GND
GND
VCC
TMS
TRST
BM
FS1
VCC
GND
GND
GND
GND
GND
GND
VCC
TCK
TDI
EF RCLK
ASYR
IP
BE
PAE
VCC
VCC
GND VCC
GND VCC
GND VCC
GND VCC
VCC
VCC
TDO
Q2
Q0
Q3
Q1
Q4
REN
PFM
RM
Q29
Q26
Q23
Q22
Q19
Q16
Q13
Q5
Q6
OE
RT
Q32
Q30
Q27
Q24
Q21
Q18
Q15
Q12
Q10
Q7
Q35
Q34
Q3
3
Q31
Q28
Q25
Q20
Q17
Q14
Q11
Q9
Q8
1
2
3
4
5
6
7
8
9
10 11
12
4667 drw02b
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
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