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IDT72V3640L10BBI

3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

BIG-ENDIAN/LITTLE-ENDIAN ( BE )

During Master Reset, a LOW on BE will select Big-Endian operation. A

HIGH on BE during Master Reset will select Little-Endian format. This function

is useful when the following input to output bus widths are implemented: x36 to

x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then

the most significant byte (word) of the long word written into the FIFO will be read

out of the FIFO first, followed by the least significant byte. If Little-Endian format

is selected, then the least significant byte of the long word written into the FIFO

will be read out first, followed by the most significant byte. The mode desired is

configured during master reset by the state of the Big-Endian (BE) pin. See

Figure 4 for Bus-Matching Byte Arrangement.

PROGRAMMABLE FLAG MODE (PFM)

During Master Reset, a LOW on PFM will select Asynchronous Program-

mable flag timing mode. A HIGH on PFM will select Synchronous Programmable

flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,

LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition

of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.

Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and

PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected (PFM, HIGH during

MRS) , the PAE is asserted and updated on the rising edge of RCLK only and

not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK

only and not RCLK. The mode desired is configured during master reset by the

state of the Programmable Flag Mode (PFM) pin.

INTERSPERSED PARITY (IP)

During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.

A HIGH will select Interspersed Parity mode. The IP bit function allows the user

to select the parity bit in the word loaded into the parallel port (D0-Dn) when

programming the flag offsets. If Interspersed Parity mode is selected, then the

FIFO will assume that the parity bits are located in bit position D8, D17, D26 and

D35 during the parallel programming of the flag offsets. If Non-Interspersed

Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits

and D32, D33, D34 and D35 are ignored. IP mode is selected during Master

Reset by the state of the IP input pin. Interspersed Parity control only has an

effect during parallel programming of the offset registers. It does not effect the data

written to and read from the FIFO.

OUTPUTS:

FULL FLAG ( FF/IR )

This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function

is selected. When the FIFO is full, FF will go LOW, inhibiting further write

operations. When FF is HIGH, the FIFO is not full. If no reads are performed

after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO

(D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the

IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and

32,768 for the IDT72V3690. See Figure 7, Write Cycle and Full Flag Timing

(IDT Standard Mode), for the relevant timing information.

In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW

when memory space is available for writing in data. When there is no longer

any free space left, IR goes HIGH, inhibiting further write operations. If no reads

are performed after a reset (either MRS or PRS), IR will go HIGH after D writes

to the FIFO (D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097

for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680

and 32,769 for the IDT72V3690. See Figure 9, Write Timing (FWFT Mode),

for the relevant timing information.

The IR status not only measures the contents of the FIFO memory, but also

counts the presence of a word in the output register. Thus, in FWFT mode, the

total number of writes necessary to deassert IR is one greater than needed to

assert FF in IDT Standard mode.

FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are

double register-buffered outputs.

EMPTY FLAG ( EF/OR )

This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)

function is selected. When the FIFO is empty, EF will go LOW, inhibiting further

read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read

Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for

the relevant timing information.

In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW

at the same time that the first word written to an empty FIFO appears valid on

the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts

the last word from the FIFO memory to the outputs. OR goes HIGH only with

a true read (RCLK with REN = LOW). The previous data stays at the outputs,

indicating the last word was read. Further data reads are inhibited until OR goes

LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing

information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode, OR is a triple register-buffered output.

PROGRAMMABLE ALMOST-FULL FLAG ( PAF )

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reaches the almost-full condition. In IDT Standard mode, if no reads are

performed after reset (MRS), PAF will go LOW after (D - m) words are written

to the FIFO. The PAF will go LOW after (1,024-m) writes for the IDT72V3640,

(2,048-m) writes for the IDT72V3650, (4,096-m) writes for the IDT72V3660,

(8,192-m) writes for the IDT72V3670, (16,384-m) writes for the IDT72V3680

and (32,768-m) writes for the IDT72V3690. The offset “m” is the full offset value.

The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the PAF will go LOW after (1,025-m) writes for the

IDT72V3640, (2,049-m) writes for the IDT72V3650, (4,097-m) writes for the

IDT72V3660 and (8,193-m) writes for the IDT72V3670, (16,385-m) writes for

the IDT72V3680 and (32,769-m) writes for the IDT72V3690, where m is the

full offset value. The default setting for this value is stated in Table 2.

See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT

Standard and FWFT Mode), for the relevant timing information.

If asynchronous PAF configuration is selected, the PAF is asserted LOW

on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH

on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF

configuration is selected, the PAF is updated on the rising edge of WCLK. See

Figure 20, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT

Mode).

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO

reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW

when there are n words or less in the FIFO. The offset “n” is the empty offset

value. The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in Table 2.

See Figure 19, Synchronous Programmable Almost-Empty Flag Timing

(IDT Standard and FWFT Mode), for the relevant timing information.

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