IDT72T3645L4-4BB Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72T3645L4-4BB

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

Integrated Device Technology 

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync 36-BIT FIFO

1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol

Name

I/O TYPE

Description

PRS PartialReset

Q0–Q35 DataOutputs

RCLK/ Read Clock/

RD Read Stobe

RCS Read Chip Select

REN Read Enable

RHSTL(1) Read Port HSTL

Select

RT Retransmit

SCLK Serial Clock

SEN Serial Enable

SHSTL SystemHSTL

Select

TCK(2) JTAG Clock

TDI(2) JTAG Test Data

Input

TDO(2) JTAG Test Data

Output

TMS(2) JTAG Mode

Select

TRST(2) JTAG Reset

WEN WriteEnable

WCS WriteChipSelect

WCLK/ WriteClock/

WR WriteStrobe

HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,

INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings

are all retained.

HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not

OUTPUT be connected. Outputs are not 5V tolerant regardless of the state of OE and RCS.

HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled byREN, the rising edge of RCLK

INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values

loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read

port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN

should be tied LOW.

HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During

INPUT aMasterResetorPartialResettheRCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance

regardless of RCS.

HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enablesRCLK for reading data from the

INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN

input should be tied LOW.

LVTTL This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are

INPUT required, this input must be tied HIGH. Otherwise it should be tied LOW.

HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to

INPUT HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode

or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump

to the ‘mark’ location.

HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that

INPUT SEN is enabled.

HSTL-LVTTL SENenables serial loading of programmable flag offsets.

INPUT

LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.

INPUT

HSTL-LVTTL ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperations

INPUT of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and

outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.

HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,

INPUT test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register

and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.

HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,

OUTPUT test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID

Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and

SHIFT-IR controller states.

HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the

INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically

INPUT reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.

If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG

function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper

FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.

HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into

INPUT theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the

WEN input should be tied LOW.

HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.

INPUT

HSTL-LVTTL IfSynchronousoperationofthewriteporthasbeenselected,whenenabledbyWEN,therisingedgeofWCLK

INPUT writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into

the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).

8

Share Link: