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IDT72T36125

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

Integrated Device Technology 

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync 36-BIT FIFO

1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

This device includes a Retransmit from Mark feature that utilizes two control

inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect

to the RCLK, the memory location being read at that point will be marked. Any

subsequent retransmit operation, RT goes LOW, will reset the read pointer to

this ‘marked’ location.

The device can be configured with different input and output bus widths as

shown in Table 1.

A Big-Endian/Little-Endian data word format is provided. This function is

useful when data is written into the FIFO in long word format (x36/x18) and read

out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,

then the most significant byte (word) of the long word written into the FIFO will

be read out of the FIFO first, followed by the least significant byte. If Little-Endian

format is selected, then the least significant byte of the long word written into the

FIFO will be read out first, followed by the most significant byte. The mode desired

is configured during master reset by the state of the Big-Endian (BE) pin. See

Figure 5 for Bus-Matching Byte Arrangement.

The Interspersed/Non-Interspersed Parity (IP) bit function allows the user

to select the parity bit in the word loaded into the parallel port (D0-Dn) when

programming the flag offsets. If Interspersed Parity mode is selected, then the

FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and

D35 during the parallel programming of the flag offsets. If Non-Interspersed

Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits

and D32, D33, D34 and D35 are ignored. IP mode is selected during Master

Reset by the state of the IP input pin.

If, at any time, the FIFO is not actively performing an operation, the chip will

automatically power down. Once in the power down state, the standby supply

current consumption is minimized. Initiating any operation (by activating control

inputs) will immediately take the device out of the power down state.

Both an Asynchronous Output Enable pin (OE) and Synchronous Read

Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip

Select is synchronized to the RCLK. Both the output enable and read chip select

control the output buffer of the FIFO, causing the buffer to be either HIGH

impedance or LOW impedance.

A JTAG test port is provided, here the FIFO has fully functional Boundary

Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and

Boundary Scan Architecture.

The TeraSync FIFO has the capability of operating its ports (write and/or

read) in either LVTTL or HSTL mode, each ports selection independent of the

other. The write port selection is made via WHSTL and the read port selection

via RHSTL. An additional input SHSTL is also provided, this allows the user

to select HSTL operation for other pins on the device (not associated with the

write or read ports).

The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/

72T36105/72T36115/72T36125 are fabricated using IDT’s high speed sub-

micron CMOS technology.

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