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IDT723676L12PF

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

Integrated Device Technology 

IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH

BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

Symbol

Parameter

Commercial

IDT723656L12 IDT723656L15

IDT723666L12 IDT723666L15

IDT723676L12 IDT723676L15

Min. Max. Min. Max. Unit

fS

Clock Frequency, CLKA, CLKB, or CLKC

—

83 — 66.7 MHz

tCLK

Clock Cycle Time, CLKA, CLKB, or CLKC

12

—

15 —

ns

tCLKH

Pulse Duration, CLKA, CLKB, or CLKC HIGH

5

—

6—

ns

tCLKL

Pulse Duration, CLKA, CLKB, OR CLKC LOW

5

—

6—

ns

tDS

Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑

tENS1

Setup Time, CSA and W/RA before CLKA↑; CSB before CLKB↑

3

—

4—

ns

4

— 4.5 —

ns

tENS2

Setup Time, ENA, and MBA before CLKA↑; RENB and MBB before CLKB↑;

WENC and MBC before CLKC↑

3

— 4.5 —

ns

tRSTS

Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW before CLKA↑ or CLKB↑(1) 5

—

5—

ns

tFSS

Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH

7.5

— 7.5 —

ns

tBES

Setup Time, BE/FWFT before MRS1 and MRS2 HIGH

7.5

— 7.5 —

ns

tSDS

tSENS

tFWS

tRTMS

Setup Time, FS0/SD before CLKA↑

Setup Time, FS1/SEN before CLKA↑

Setup Time, BE/FWFT before CLKA↑

Setup Time, RTM before RT1; RTM before RT2

3

—

4—

ns

3

—

4—

ns

0

—

0—

ns

5

—

5—

ns

tDH

Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑

0.5

—

1—

ns

tENH

Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, RENB, and MBB after

CLKB↑; WENC and MBC after CLKC↑

0.5

—

1—

ns

tRSTH

Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW after CLKA↑ or CLKB↑(1)

4

—

4—

ns

tFSH

Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH

2

—

2—

ns

tBEH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

2

—

2—

ns

tSDH

Hold Time, FS0/SD after CLKA↑

0.5

—

1—

ns

tSENH

Hold Time, FS1/SEN HIGH after CLKA↑

0.5

—

1—

ns

tSPH

Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH

2

—

2—

ns

tRTMH Hold Time, RTM after RT1; RTM after RT2

5

—

5—

ns

tSKEW1(2) Skew Time, between CLKA↑ and CLKB↑ for EFB/ORB and FFA/IRA; between CLKA↑ 5

— 7.5 —

ns

and CLKC↑ for EFA/ORA and FFC/IRC

tSKEW2(2,3) Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA; between CLKA↑ and

CLKC↑ for AEA and AFC

12

—

12 —

ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.

3. Design simulated, not tested.

4. Industrial temperature range is available by special order.

9

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