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IDT723674

CMOS SyncBiFIFO™ WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

Integrated Device Technology 

IDT723654/723664/723674 CMOS SyncBiFIFOTM WITH BUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723654/723664/723674 with CLKA

and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected

to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL

HIGH levels are known, the power dissipation can be calculated with the equation below.

CALCULATING POWER DISSIPATION

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x ICC(f) + Σ(CL x VCC2 x fo)

N

where:

N = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)

CL = outputcapacitanceload

fo = switching frequency of an output

300

250

200

150

100

50

0

0

fdata = 1/2 fS

TA = 25oC

CL = 0 pF

VCC = 5.0V

VCC = 5.5V

VCC = 4.5V

10

20

30

40

50

60

70

fS  Clock Frequency  MHz

80

90

5608drw03

Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

8

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