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IDT723652 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723652 Datasheet PDF : 29 Pages
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IDT723652/723662/723672 CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Symbol
Parameter
fS
Clock Frequency, CLKA or CLKB
tCLK
Clock Cycle Time, CLKA or CLKB
tCLKH
Pulse Duration, CLKA or CLKB HIGH
tCLKL
Pulse Duration, CLKA and CLKB LOW
tDS
Setup Time, A0-A35 before CLKAand B0-B35 before CLKB
tENS1
Setup Time, CSA and W/RA, before CLKA; CSB, and W/RB before CLKB
tENS2
Setup Time, ENA and MBA, before CLKA; ENB, and MBB before CLKB
tRSTS
Setup Time, RST1 or RST2 LOW before CLKAor CLKB(1)
tFSS
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
tFWS
Setup Time, FWFT before CLKA
tDH
Hold Time, A0-A35 after CLKAand B0-B35 after CLKB
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and
MBB after CLKB
tRSTH
Hold Time, RST1 or RST2 LOW after CLKAor CLKB(1)
tFSH
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
tSKEW1(2) Skew Time, between CLKAand CLKBfor EFA/ORA, EFB/ORB, FFA/IRA,
and FFB/IRB
tSKEW2(2,3) Skew Time, between CLKAand CLKBfor AEA, AEB, AFA, and AFB
Commercial
IDT723652L12
IDT723662L12
IDT723652L15
IDT723662L15
IDT723672L12
IDT723672L15
Min.
Max.
Min.
Max. Unit
83
66.7 MHz
12
15
ns
5
6
ns
5
6
ns
3
4
ns
4
4.5
ns
3
4.5
ns
5
5
ns
7.5
7.5
ns
0
0
ns
0.5
1
ns
0.5
1
ns
4
4
ns
2
2
ns
7.5
7.5
ns
12
12
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
4. Industrial temperature range is available by special order.
8

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