IDT723631(2002) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723631 Datasheet PDF : 21 Pages
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IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
250
fdata = 1/2 fS
TA = 25°C
CL = 0pF
200
150
VCC = 5.0V
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
VCC = 5.5V
VCC= 4.5V
100
50
0
0
10
20
30
40
50
fS Clock Frequency MHz
Figure 1. Typical Characteristics: Supply vs Clock Frequency
60
70
3023 drw04
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723641 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to
normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT723631/723641/723651
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC2 x fO)
where:
N = number of inputs driven by TTL levels
∆ICC = increase in power supply current for each input at a TTL HIGH level
dc = duty cycle of inputs at a TTL HIGH level of 3.4
CL = output capacitance load
fO = switching frequency of an output
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.209 mA/MHz
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