IDT723631(2002) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723631 Datasheet PDF : 21 Pages
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IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
register has a flag to signal when new mail has been stored. Two or more
devices may be used in parallel to create wider data paths. Expansion is
also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the
LOW-to-HIGH transition of a continuous (free-running) port clock by en-
able signals. The continuous clocks for each port are independent of one
another and can be asynchronous or coincident. The enables for each
port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are
two-stage synchronized to CLKA. The Output Ready (OR) flag and Al-
most-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB.
Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be
programmed from port A or through a serial input.
PIN CONFIGURATION
NC 18
B35 19
*
B34 20
B33 21
B32 22
GND 23
B31 24
B30 25
B29 26
B28 27
B27 28
B26 29
VCC 30
B25 31
B24 32
GND 33
B23 34
B22 35
B21 36
B20 37
B19 38
B18 39
GND 40
B17 41
B16 42
VCC 43
B15 44
B14 45
B13 46
B12 47
GND 48
NC 49
NC 50
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES:
1. NC – No Connection
2. Uses Yamaichi socket IC51-1324-828
PQFP (PQ132-1, ORDER CODE: PQF)
TOP VIEW
2
116 NC
115 NC
114 A35
113 A34
112 A33
111 A32
110 VCC
109 A31
108 A30
107 GND
106 A29
105 A28
104 A27
103 A26
102 A25
101 A24
100 A23
99 GND
98 A22
97 VCC
96 A21
95 A20
94 A19
93 A18
92 GND
91 A17
90 A16
89 A15
88 A14
87 A13
86 VCC
85 A12
84 NC
3023 drw02
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