IDT723631(2002) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723631
(Rev.:2002)

CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36

Integrated Device Technology 

CMOS SyncFIFO™

512 x 36

1,024 x 36

2,048 x 36

IDT723631

IDT723641

IDT723651

FEATURES:

• Storage capacity:

IDT723631 - 512 x 36

IDT723641 - 1,024 x 36

IDT723651 - 2,048 x 36

• Supports clock frequencies up to 67 MHz

• Fast access times of 11ns

• Free-running CLKA and CLKB can be asynchronous or coinci-

dent (permits simultaneous reading and writing of data on a

single clock edge)

• Clocked FIFO buffering data from Port A to Port B

• Synchronous read retransmit capability

• Mailbox register in each direction

• Programmable Almost-Full and Almost-Empty flags

• Microprocessor interface control logic

• Input Ready (IR) and Almost-Full (AF) flags synchronized by

CLKA

• Output Ready (OR) and Almost-Empty (AE) flags synchronized

by CLKB

• Available in 132-pin plastic quad flat package (PQFP) or space-

saving 120-pin thin quad flat package (TQFP)

• Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT723631/723641/723651 is a monolithic high-speed, low-power,

CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz

and has read access times as fast as 12ns. The 512/1,024/2,048 x 36

dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory

has retransmit capability, which allows previously read data to be ac-

cessed again. The FIFO has flags to indicate empty and full conditions and

two programmable flags (Almost-Full and Almost-Empty) to indicate when a

selected number of words is stored in memory. Communication between

each port may take place with two 36-bit mailbox registers. Each mailbox

FUNCTIONAL BLOCK DIAGRAM

MBF1

CLKA

CSA

W/RA

ENA

MBA

Port-A

Control

Logic

RST

Reset

Logic

36

A0 - A35

IR

AF

Mail 1

Register

RAM ARRAY

512 x 36

1,024 x 36

2,048 x 36

Write Read

Pointer Pointer

Status Flag

Logic

RTM

RFM

B0 - B35

OR

AE

FS0/SD

FS1/SEN

Flag Offset

10

Registers

Mail 2

Register

MBF2

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

1

2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

Port-B

Control

Logic

CLKB

CSB

W/RB

ENB

MBB

3023 drw01

SEPTEMBER 2002

DSC-2023/5

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