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IDT723613

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol

Name

I/O

Description

PGA

Port A Parity Generation

I

Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity

generated is selected by the state of the ODD/EVEN input. Bytes are organized at A0-A8, A9-A17,

A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.

PGB

Port B Parity

RST

Reset

I

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is

selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and

B27-B35. The generated parity bits are output in the most significant bit of each byte.

I

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB

must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF

flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select

Almost-Full flag and Almost-Empty flag offset.

SIZ0,

Port B Bus Size Selects

I

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to

SIZ1

(Port B) HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be

long word, word, or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit

write or read.

SW0,

SW1

Port B Byte Swap Selects

I

(Port B)

At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by

SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte order

swapping is possible with any bus-size selection.

W/RA

W/RB

Port A Write/Read Select

Select

Port B Write/Read Select

I

A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH

transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.

I

A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH

transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.

5

JANUARY 14, 2009

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