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IDT723613L20PF

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36

TABLE 3 — PORT B ENABLE FUNCTION TABLE

CSB

W/RB

ENB

SIZ1, SIZ0

CLKB

B0-B35 Outputs

H

X

X

X

X

In high-impedance state

L

H

L

X

X

In high-impedance state

L

H

H

One, both LOW

↑

In high-impedance state

L

H

H

Both HIGH

↑

In high-impedance state

L

L

L

One, both LOW

X

Active, FIFO output register

L

L

H

One, both LOW

↑

Active, FIFO output register

L

L

L

Both HIGH

X

Active, mail1 register

L

L

H

Both HIGH

↑

Active mail1 register

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Port Function

None

None

None

Mail2 write

None

FIFO read

None

Mail1 read (set MBF1 HIGH)

(CLKA). When the FF is HIGH, a SRAM location is free to receive new data.

No memory locations are free when the FF is LOW and attempted writes to the

FIFO are ignored.

Each time a word is written to the FIFO, its write-pointer is incremented. The

state machine that controls the FF monitors a write-pointer and read-pointer

comparator that indicates when the FIFO SRAM status is full, full-1, or full-2.

From the time a word is read from the FIFO, its previous memory location is ready

to be written in a minimum of three CLKA cycles. Therefore, a FF is LOW if less

than two CLKA cycles have elapsed since the next memory write location has

been read. The second LOW-to-HIGH transition on the FF synchronizing clock

after the read sets the FF HIGH and data can be written in the following clock

cycle.

A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of

a read if the clock transition occurs at time tSKEW1 or greater after the read.

Otherwise, the subsequent clock cycle can be the first synchronization cycle

(see Figure 11).

ALMOST-EMPTY FLAG (AE)

The FIFO Almost-Empty flag is synchronized to the port clock that reads data

from its array (CLKB). The state machine that controls the AE flag monitors a

write-pointer and read-pointer comparator that indicates when the FIFO SRAM

status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty

state is defined by the value of the Almost-Full and Almost-Empty Offset register

(X). This register is loaded with one of four preset values during a device reset

(see reset above). The AE flag is LOW when the FIFO contains X or less long

words in memory and is HIGH when the FIFO contains (X+1) or more long

words.

Two LOW-to-HIGH transitions on the port B Clock (CLKB) are required after

a FIFO write for the AE flag to reflect the new level of fill. Therefore, the AE flag

of a FIFO containing (X+1) or more long words remains LOW if two CLKB cycles

TABLE 4 — FIFO FLAG OPERATION

Number of 36-Bit

Words in the FIFO(1)

0

1 to X

(X + 1) to [64 – (X + 1)]

(64 – X) to 63

64

Synchronized

to CLKB

EF

AE

L

L

H

L

H

H

H

H

H

H

Synchronized

to CLKA

AF

FF

H

H

H

H

H

H

L

H

L

L

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.

have not elapsed since the write that filled the memory to the (X+1) level. The

AE flag is set HIGH by the second CLKB LOW-to-HIGH transition after the FIFO

write that fills memory to the (X+1) level. A LOW-to-HIGH transition of CLKB

begins the first synchronization cycle if it occurs at time tSKEW2 or greater after

the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent CLKB

cycle can be the first synchronization cycle (see Figure 12).

ALMOST FULL FLAG (AF)

The FIFO Almost-Full flag is synchronized to the port clock that writes data

to its array (CLKA). The state machine that controls an AF flag monitors a write-

pointer and read-pointer comparator that indicates when the FIFO SRAM status

is almost -full, almost- full-1, or almost-full-2. The almost-full state is defined by

the value of the Almost-Full and Almost-Empty Offset register (X). This register

is loaded with one of four preset values during a device reset (see reset above).

The AF flag is LOW when the FIFO contains (64-X) or more long words in

memory and is HIGH when the FIFO contains [64-(X+1)] or less long words.

Two LOW-to-HIGH transitions on the port A Clock (CLKA) are required after

a FIFO read for the AF flag to reflect the new level of fill. Therefore, the AF flag

of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA cycles

have not elapsed since the read that reduced the number of long words in

memory to [64-(X+1)]. The AF flag is set HIGH by the second CLKA LOW-to-

HIGH transition after the FIFO read that reduces the number of long words in

memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first

synchronization cycle if it occurs at time tSKEW2 or greater after the read that

reduces the number of long words in memory to [64-(X+1)]. Otherwise, the

subsequent CLKA cycle can be the first synchronization cycle (see Figure 13).

MAILBOX REGISTERS

Two 36-bit bypass registers (mail1, mail2) are on the IDT723613 to pass

command and control information between port A and port B without putting it

in queue. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1

register when a port A write is selected by CSA, W/RA, and ENA (with MBA

HIGH). A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2

register when a port B write is selected by CSB, W/RB, and ENB (and both SIZ0

and SIZ1 are HIGH). Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while

its mail flag is LOW.

When the port B data (B0-B35) outputs are active, the data on the bus comes

from the FIFO output register when either one or both SIZ1 and SIZ0 are LOW

and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1

Register Flag (MBF1) is set HIGH by a rising CLKB edge when a port B read

is selected by CSB, W/RB, and ENB, (and both SIZ1 and SIZ0 HIGH). The

Mail2 Register Flag (MBF2) is set HIGH by a rising CLKA edge when a port

A read is selected by CSA, W/RA, and ENA (with MBA HIGH). The data in a

mail register remains intact after it is read and changes only when new data is

11

JANUARY 14, 2009

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