IDT723611(1999) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723611
(Rev.:1999)

CMOS SyncFIFO™ 64 x 36

Integrated Device Technology 

IDT723611

400

350

300

250

200

150

100

50

0

0

fdata = 1/2 fS

TA = 25°C

CL = 0 pF

Commercial Temperature Range

VCC = 5.0V

VCC = 5.5V

VCC = 4.5V

10

20

30

40

50

60

fclock  Clock Frequency  MHz

Figure 1. Typical Characteristics: Supply Current vs Clock Frequency

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3024 drw 04

CALCULATING POWER DISSIPATION

The ICC(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT723611 with CLKA and CLKB operating at

frequency fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were discon-

nected to normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be

calculated with the equation below.

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723611 may be calculated by:

PT = VCC x ICC(f) + Σ(CL x VOH - VOL)2 X fO)

where:

CL =

fO =

output capacitance load

switching frequency of an output

VOH =

output high-level voltage

VOL =

output low-level voltage

When no read or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is

calculated by:

PT = VCC x fS x 0.290 mA/MHz

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