IDT723611(1999) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723611 Datasheet PDF : 19 Pages
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IDT723611
Commercial Temperature Range
SIGNAL DESCRIPTION
RESET ( RST )
The IDT723611 is reset by taking the Reset (RST) input LOW for at least
four port-A clock (CLKA) and four port-B clock (CLKB) LOW-to-HIGH transi-
tions. The reset input can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers of the FIFO and forces the Full Flag
(FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty flag (AE) LOW, and the
Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2)
HIGH. Afterareset,FFissetHIGHaftertwoLOW-to-HIGHtransitionsofCLKA.
The device must be reset after power up before data is written to its memory.
A LOW-to-HIGH transition on the RSTinput loads the Almost-Full and Almost-
Empty Offset register (X) with the value selected by the Flag Select (FS0, FS1)
inputs. The values that can be loaded into the register are shown in Table 1.
Almost-Full and
Almost-Empty Flag
Offset Register (X)
FS1
FS0
RST
16
H
H
↑
12
H
L
↑
8
L
H
↑
4
L
L
↑
Table 1. Flag Programming
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-A Chip
Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs
are in the high-impedance state when either CSA or W/RA is HIGH. The A0-
A35outputsareactivewhenbothCSAandW/RAareLOW. Dataisloadedinto
the FIFO from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when
CSAis LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFis HIGH (see
Table 2).
The port-B control signals are identical to those of port A. The state of the
port-B data (B0-B35) outputs is controlled by the port-B Chip Select (CSB) and
the port-B Write/Read select (W/RB). The B0-B35 outputs are in the high-
impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are
active when both CSB and W/RB are LOW. Data is read from the FIFO to the
B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/
RB is LOW, ENB is HIGH, MBB is LOW, and EF is HIGH (see Table 3).
The setup and hold-time constraints to the port clocks for the port Chip
Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling
write and read operations and are not related to HIGH-impedance control of
the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip
Select and Write/Read select can change states during the setup and hold-time
window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO flag is synchronized to its port clock through two flip-flop stages.
This is done to improve the flags’ reliability by reducing the probability of
mestastable events on their outputs when CLKA and CLKB operate asynchro-
CSA
W/RA
ENA
MBA CLKA
A0-A35 Outputs
H
X
X
X
X
In High-Impedance State
L
H
L
X
X
In High-Impedance State
L
H
H
L
↑
In High-Impedance State
L
H
H
H
↑
In High-Impedance State
L
L
L
L
X
Active, Mail2 Register
L
L
H
L
↑
Active, Mail2 Register
L
L
L
H
X
Active, Mail2 Register
L
L
H
H
↑
Active, Mail2 Register
Table 2. Port-A Enable Function Table
CSB
W/RB
ENB
MBB CLKB
B0-B35 Outputs
H
X
X
X
X
In High-Impedance State
L
H
L
X
X
In High-Impedance State
L
H
H
L
↑
In High-Impedance State
L
H
H
H
↑
In High-Impedance State
L
L
L
L
X
Active, FIFO Output Register
L
L
H
L
↑
Active, FIFO Output Register
L
L
L
H
X
Active, Mail1 Register
L
L
H
H
↑
Active, Mail1 Register
Table 3. Port-B Enable Function Table
10
Port Functions
None
None
FIFO Write
Mail1 Write
None
None
None
Mail2 Read (set MBF2 HIGH)
Port Functions
None
None
None
Mail2 Write
None
FIFO Read
None
Mail1 Read (set MBF1 HIGH)
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