IDT7202LA35J(1997) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT7202LA35J
(Rev.:1997)

CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1,024 x 9

Integrated Device Technology 

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

LAST READ

IGNORED

READ

FIRST WRITE

ADDITIONAL FIRST

WRITES

READ

W

R

EF

DATA OUT

t REF

tWEF

tA

VALID

VALID

Figure 5. Empty Flag From Last Read to First Write

2679 drw 07

RT

W,R

HF, EF, FF

t RTC

t RT

t RTS

t RTF

Figure 6. Retransmit

t RTR

FLAG VALID

2679 drw 08

W

t WEF

EF

t RPE

R

2679 drw 09

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse

R

t RFF

FF

t WPF

W

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse

2679 drw 10

8

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