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IDT71V428L

3.3V CMOS Static RAM 4 Meg (1M x 4-Bit)

Integrated Device Technology 

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM

4 Meg (1M x 4-Bit)

Timing Waveform of Read Cycle No. 1(1)

ADDRESS

tRC

tAA

OE

CS

DATAOUT

tOE

tOLZ (5)

tCLZ (5)

tACS (3)

HIGH IMPEDANCE

tPU

VDD SUPPLY ICC

CURRENT ISB

Commercial and Industrial Temperature Ranges

tOHZ (5)

tCHZ (5)

DATAOUT VALID

tPD

3623 drw 06

Timing Waveform of Read Cycle No. 2(1,2,4)

ADDRESS

DATAOUT

tRC

tAA

tOH

PREVIOUS DATAOUT VALID

tOH

DATAOUT VALID

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

3623 drw 07

6.642

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