IDT71V428L12YG Просмотр технического описания (PDF) - Integrated Device Technology
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IDT71V428L12YG Datasheet PDF : 9 Pages
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IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Pin Configuration
A0
A1
A2
A3
A4
CS
I/O 0
VDD
VSS
I/O 1
WE
A5
A6
A7
A8
A9
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
SO32-3
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
A19
A18
A17
A16
A15
OE
I/O 3
VSS
VDD
I/O 2
A14
A13
A12
A11
A10
NC
SOJ
3623 drw 02
Top View
Commercial and Industrial Temperature Ranges
Pin Description
A0 – A19
CS
WE
OE
I/O0 - I/O3
VDD
VSS
Address Inputs
Chip Select
Write Enable
Output Enable
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
I/O
Power
Gnd
3623 tbl 02
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter(1)
Conditions Max. Unit
CIN Input Capacitance
VIN = 3dV
7 pF
CI/O I/O Capacitance
VOUT = 3dV
8 pF
NOTE:
3623 tbl 03
1. This parameter is guaranteed by device characterization, but not production tested.
Truth Table(1,2)
CS
OE
WE
I/O
Function
L
L
H
DATAOUT Read Data
L
X
L
DATAIN Write Data
L
H
H
High-Z Output Disabled
H
X
X
High-Z Deselected - Standby (ISB)
VHC(3 )
X
X
High-Z Deselected - Standby (ISB1)
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥VHC or ≤VLC.
3623 tbl 01
6.242
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