IDT71342LA Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT71342LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

Integrated Device Technology 

IDT71342SA/LA

High-Speed 4K x 8 Dual-Port Static RAM with Semaphore

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read After Write Timing, Either Side(1)

tSAA

tOH

A0 - A2

VALID ADDRESS

VALID ADDRESS

SEM

tAW

tWR

tEW

tACE

DATA0

R/W

tDW

DATAIN VALID

tAS

tWP

tDH

tSOP

DATAOUT

VALID

tSWRD

tAOE

OE

tSOP

Write Cycle

Test Cycle

(Read Cycle)

2721 drw 12

NOTE:

1. CE = VIH for the duration of the above timing (both write and read cycle).

Timing Waveform of Semaphore Condition(1,3,4)

A0"A" - A2"A"

MATCH

SIDE(2) "A"

R/W"A"

SEM"A"

A0"B" - A2"B"

tSPS

MATCH

SIDE(2) "B"

R/W"B"

SEM"B"

2721 drw 13

NOTES:

1. D0R = D0L = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

3. This parameter is measured from the point where R/W "A" or SEM "A" goes HIGH until R/W "B" or SEM "B" goes HIGH.

4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

61.402

Share Link: