IDT71024S12YI Просмотр технического описания (PDF) - Integrated Device Technology

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IDT71024S12YI

CMOS Static RAM 1 Meg (128K x 8-Bit)

Integrated Device Technology 

IDT71024 CMOS Static RAM

1 Meg (128K x 8-Bit)

Timing Waveform of Write Cycle No. 1

(WE Controlled Timing)(1,4,6)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2

(CS1 AND CS2 Controlled Timing)(1,4)

NOTES:

1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.

2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after theWE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must

both be active during the tCW write period.

5. Transition is measured ±200mV from steady state.

6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.

6.462

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