IDT7018L Просмотр технического описания (PDF) - Integrated Device Technology
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IDT7018L Datasheet PDF : 17 Pages
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IDT7018L
High-Speed 64K x 9 Dual-Port Static RAM
Truth Table I: Chip Enable(1,2)
CE
CE0
CE1
Industrial and Commercial Temperature Ranges
Mode
VIL
VIH
Port Selected (TTL Active)
L
< 0.2V
>VCC -0.2V Port Selected (CMOS Active)
VIH
X
Port Deselected (TTL Inactive)
X
H
>VCC -0.2V
VIL
Port Deselected (TTL Inactive)
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or > VCC - 0.2V.
4841 tbl 06
Truth Table II: Non-Contention Read/Write Control
Inputs(1)
Outputs
CE(2) R/W OE SEM
I/O0-8
Mode
H
X
X
H
High-Z Deselected: Power-Down
L
L
X
H
DATAIN Write to memory
L
H
L
H
DATAOUT Read memory
X
X
H
X
High-Z Outputs Disabled
NOTES:
1. A0L – A15L ≠ A0R – A15R.
2. Refer to Chip Enable Truth Table.
4841 drw 07
Truth Table III: Semaphore Read/Write Control(1)
Inputs
Outputs
CE(2) R/W OE SEM
I/O0-8
Mode
H
H
L
L DATAOUT Read Semaphore Flag Data Out
H↑
X
L
DATAIN Write I/O0 into Semaphore Flag
L
X
X
L
______
Not Allowed
NOTES:
1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O8). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
4841 tbl 08
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