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6116LA120

CMOS STATIC RAM 16K (2K x 8 BIT)

Integrated Device Technology 

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1(1, 3)

tRC

ADDRESS

tAA

OE

CS

DATA OUT

ICC

V CC

Supply

Currents

ISB

tOE

tOLZ (5)

tACS

tCLZ (5)

tPU

TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)

tRC

ADDRESS

tAA

tOH

DATA OUT

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 3 (1, 3, 4)

CS

tCLZ (5)

tACS

DATA OUT

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±500mV from steady state.

tOH

tOHZ (5)

tCHZ (5)

DATA

VALID

tPD

3089 drw 06

tOH

DATA VALID

3089 drw 07

tCHZ (5)

DATA VALID

3089 drw 08

5.1

7

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