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IDT54FCT162240AT

FAST CMOS 16-BIT BUFFER/LINE DRIVER

Integrated Device Technology 

IDT54/74FCT16240T/AT/CT/ET,162240T/AT/CT/ET

FAST CMOS 16-BIT BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

V CC

VIN

Pulse

Generator

D.U.T.

RT

VOUT

50pF

CL

500Ω

500Ω

SWITCH POSITION

7.0V

Test

Switch

Open Drain

Disable Low

Closed

Enable Low

All Other Tests

Open

DEFINITIONS:

2541 lnk 10

CL= Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

2541 drw 05

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DATA

INPUT

tSU

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

tSU

ETC.

tH

tREM

tH

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

tPLH

tPHL

OUTPUT

tPLH

tPHL

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

2541 drw 06

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

1.5V

tW

1.5V

2541 drw 07

ENABLE AND DISABLE TIMES

3V

1.5V

0V

VOH

1.5V

VOL

3V

1.5V

0V

2541 drw 08

ENABLE

DISABLE

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

tPZL

SWITCH

CLOSED

tPZH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

3V

1.5V

0V

tPLZ

3.5V

3.5V

1.5V

tPHZ

0.3V VOL

1.5V

0.3V VOH

0V

0V

NOTES:

2541 drw 09

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

5.1

7

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