IDT49FCT3805B Просмотр технического описания (PDF) - Integrated Device Technology
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IDT49FCT3805B Datasheet PDF : 7 Pages
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IDT49FCT3805B
3.3V CMOS BUFFER/CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
VCC
6V
GND
VIN
Pulse
Generator
D.U.T.
VOUT
RT
50pF
500Ω
500Ω
SWITCH POSITION
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
6V
GND
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
INPUT
OUTPUT
Test Circuits for All Outputs
tPLH
tPHL
tR
tF
Package Delay
3V
1.5V
0V
VOH
2.0V
1.5V
0.8V VOL
INPUT
OUTPUT
tPLH
tPHL
tSK(p) = |tPHL - tPLH|
Pulse Skew - tSK(P)
3V
1.5V
0V
VOH
1.5V
VOL
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
DISABLE
3V
1.5V
3.5V
1.5V
tPLZ
tPHZ
0.3V
0V
3.5V
V OL
1.5V
0V
0.3V VOH
0V
Output Skew - tSK(X)
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK(o)
tSK(o)
tPLH2
tPHL2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Output Skew - tSK(O)
INPUT
PACKAGE 1
OUTPUT
PACKAGE 2
OUTPUT
tPLH1
tPHL1
tSK(t)
tSK(t)
tPLH2
tPHL2
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
Package Skew - tSK(T)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
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