ICS94225 Просмотр технического описания (PDF) - Integrated Circuit Systems
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ICS94225 Datasheet PDF : 18 Pages
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ICS94225
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit
Description
PWD
7 Spread Spectrum enable (+/- 0.25% center spread) 0=OFF 1=ON
0
Bit 3 Bit 2
FS2
Bit 6
FS1
Bit 5
FS0
CPU,
Bit 4 SDRAM
PCI
AGP
0
0
0
0
0
133.33 33.33 66.67
0
0
0
0
1
95
31.67 63.33
0
0
0
1
0
100.99 33.66 67.33
0
0
0
1
1
115
38.33 76.67
0
0
1
0
0
100.7
33.57
67.13
0
0
1
0
1
103
34.33 68.67
0
0
1
1
0
105
35.00 70.00
0
0
1
1
1
110
36.67 73.33
0
1
0
0
0
102
34.00 68.00
0
1
0
0
1
104
34.67 69.33
0
1
0
1
0
106
35.33 70.67
0
1
0
1
1
107
35.67 71.33
0
1
1
0
0
108
36.00 72.00
0
1
1
0
1
109
36.33 72.67
6:2
0
1
1
1
0
90
30.00
60.00
0010
0
1
1
1
1
111
37.00 74.00 Note1
1
0
0
0
0
112
37.33 74.67
1
0
0
0
1
113
37.67 75.33
1
0
0
1
0
114
38.00 76.00
1
0
0
1
1
116
38.67 77.33
1
0
1
0
0
117
39.00 78.00
1
0
1
0
1
118
39.33 78.67
1
0
1
1
0
119
39.67 79.33
1
0
1
1
1
120
30.00 60.00
1
1
0
0
0
142
35.50 71.00
1
1
0
0
1
144
36.00 72.00
1
1
0
1
0
146
36.50 73.00
1
1
0
1
1
138
34.50 69.00
1
1
1
0
0
136
34.00 68.00
1
1
1
0
1
135
33.75 67.50
1
1
1
1
0
140
35.00 70.00
1
1
1
1
1
150
37.50 75.00
0 - Frequency is selected by hardware select, latched input;
1
Spread controlled by pin 29
0
1 - Frequency is selected by Bit (6:2); Spread controlled by Bit
0
0 - SDRAM_OUT Disable
1
1 - SDRAM_OUT Enable
Notes:
1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.
2. PWD = Power-Up Default
0445B—08/01/03
4
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