ICS8308AGILF Просмотр технического описания (PDF) - Integrated Circuit Systems

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ICS8308AGILF

LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS87004I

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL

ZERO DELAY CLOCK GENERATOR

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet the

VPP and VCMR input requirements. Figures 3A to 3D show inter-

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

here are examples only. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

For example in Figure 3A, the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

Zo = 50 Ohm

Zo = 50 Ohm

LVHSTL

ICS

HiPerClockS

LVHSTL Driver

3.3V

CLK

nCLK HiPerClockS

Input

R1

R2

50

50

3.3V

Zo = 50 Ohm

Zo = 50 Ohm

LVPECL

3.3V

CLK

nCLK HiPerClockS

Input

R1

R2

50

50

R3

50

FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

3.3V

R3

R4

125

125

3.3V

CLK

nCLK HiPerClockS

Input

R1

R2

84

84

3.3V

Zo = 50 Ohm

LVDS_Driv er

R1

100

Zo = 50 Ohm

3.3V

CLK

nCLK Receiv er

FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

87004AGI

www.icst.com/products/hiperclocks.html

11

REV. B JULY 25, 2005

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