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ICS8305AGI

LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8305I

LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/

LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

fMAX

Output Frequency

Ref = CLK/nCLK

Ref = LVCMOS_CLK

350

MHz

300

MHz

LVCMOS_CLK;

tpLH

Propagation Delay, NOTE 1A

Low to High

CLK, nCLK;

1.75

NOTE 1B

tsk(o) Output Skew; NOTE 2, 6

Measured on the Rising Edge

2.95

ns

40

ps

tsk(pp) Part-to-Part Skew; NOTE 3, 6

800

ps

Buffer Additive Phase Jitter, RMS;

tjit

refer to Additive Phase Jitter section,

NOTE 5

0.04

ps

tR / tF

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

100

IJ 166MHz

45

f > 166MHz

42

700

ps

55

%

58

%

tEN

Output Enable Time; NOTE 4

5

ns

tDIS

Output Disable Time; NOTE 4

5

ns

NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.

NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

NOTE 5: Driving only one input clock.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

TABLE

5C.

AC

CHARACTERISTICS,

V

DD

=

3.3V

±

5%,

V

DDO

=

1.8V

±

-0.15V,

TA

=

-40°C

TO

85°C

Symbol Parameter

Test Conditions

Minimum

fMAX

Output Frequency

Ref = CLK/nCLK

Ref = LVCMOS_CLK

LVCMOS_CLK;

tp

LH

Propagation Delay, NOTE 1A

Low to High

CLK, nCLK;

1.75

NOTE 1B

tsk(o) Output Skew; NOTE 2, 6

Measured on the Rising Edge

tsk(pp) Part-to-Part Skew; NOTE 3, 6

Buffer Additive Phase Jitter, RMS;

tjit

refer to Additive Phase Jitter section,

NOTE 5

t /t

RF

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

100

IJ 166MHz

45

f > 166MHz

42

tEN

Output Enable Time; NOTE 4

tDIS

Output Disable Time; NOTE 4

For notes, see Table 5B.

Typical

0.04

Maximum

350

300

3.7

45

900

700

55

58

5

5

Units

MHz

MHz

ns

ps

ps

ps

ps

%

%

ns

ns

8305AGI

www.icst.com/products/hiperclocks.html

6

REV. B MAY 19, 2005

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