ICS8305I Просмотр технического описания (PDF) - Integrated Circuit Systems
Номер в каталоге
Компоненты Описание
Список матч
ICS8305I
Integrated Circuit Systems
ICS8305I Datasheet PDF : 15 Pages
| |||
Integrated
Circuit
Systems, Inc.
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 9, 13
GND
Power
Power supply ground.
2
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
3
VDD
Power
Core supply pin.
Synchronizing clock enable. When LOW, the output clocks are
4
CLK_EN
Input Pullup disabled. When HIGH, output clocks are enabled.
LVCMOS / LVTTL interface levels.
5
CLK
Input Pulldown Non-inverting differential clock input.
6
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
Clock select input. When HIGH, selects CLK, nCLK inputs.
7
CLK_SEL
Input Pullup When LOW, selects LVCMOS_CLK input.
LVCMOS / LVTTL interface levels.
8
LVCMOS_CLK Input Pulldown LVCMOS / LVTTL clock input.
10, 12, 14, 16 Q3, Q2, Q1, Q0 Output
Clock outputs. LVCMOS / LVTTL interface levels.
11, 15
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
CPD
ROUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
11
pF
5
7
12
Ω
8305AGI
www.icst.com/products/hiperclocks.html
2
REV. B MAY 19, 2005
Share Link: