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IC61LV2568

256K x 8 Hight Speed SRAM with 3.3V

Integrated Circuit Solution Inc 

IC61LV2568

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol Parameter

-8 ns

-10 ns

-12 ns

-15 ns

Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time

tSCE CE to Write End

8—

10 —

12 —

15 —

ns

7—

8—

9 — 10 — ns

tAW Address Setup Time

to Write End

7—

8—

9 — 10 — ns

tHA Address Hold

from Write End

0—

0—

0—

0 — ns

tSA Address Setup Time

tPWE(4) WE Pulse Width

0—

7—

0—

8—

0—

0 — ns

9 — 10 — ns

tSD Data Setup to Write End

4.5 —

5—

6—

7 — ns

tHD

tHZWE(3)

tLZWE(3)

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

0—

0—

0—

0 — ns

—3

—4

—5

—6

ns

0—

0—

0—

0 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3.0V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing

are referenced to the rising or falling edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%

tested.

4.Tested with OE Hith.

AC WAVEFORMS

WRITE CYCLE NO. 1 (1,2 )(CE Controlled, OE is HIGH or LOW)

ADDRESS

CE

WE

DOUT

DIN

t WC

VALID ADDRESS

t SA

t SCE

t HA

DATA UNDEFINED

t AW

t PWE1

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

Integrated Circuit Solution, Inc.

7

AHSR023-0A 09/12/2001

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