HYB3164805AT-60 Просмотр технического описания (PDF) - Siemens AG

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HYB3164805AT-60

8M x 8-Bit Dynamic RAM (4k & 8k Refresh, EDO-Version)

Siemens AG 

HYB3164(5)805AJ/AT(L)-40/-50/-60

8M x 8-DRAM

I/O1 I/O2

I/O8

WE

. CAS

&

No. 2 Clock

Generator

Data in

Buffer

8

Data out

Buffer

OE

8

Column

11 Address

A0

Buffer(11)

A1

11

Column

Decoder

A2

A3

Refresh

A4

Controller

A5

Sense Amplifier 8

I/O Gating

A6

A7

Refresh

A8

Counter (12)

A9

A10

12

2048

x8

A11

Row

Row

Memory Array

12 Address

Buffers(12)

12 Decoder 4096 4096 x 2048 x 8

RAS

No. 1 Clock

Generator

Block Diagram for HYB 3165805AJ/AT(L)

Semiconductor Group

6

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