BR93LC66RF Просмотр технического описания (PDF) - ROHM Semiconductor

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BR93LC66RF

4,096-Bit Serial Electrically Erasable PROM

ROHM Semiconductor 

Memory ICs

BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV

(6) Connecting DI and DO directly

The BR93LC66 have an independent input pin (DI) and

output pin (DO). These are treated as individual signals

on the timing chart but can be controlled through one

control line.

Control can be initiated on a single control line by

inserting a resistor R.

µ - COM

BR93LC66

I / O PORT

DI

R

DO

Fig.11 Common connections for

the DI and DO control line

1) Data collision between the µ-COM output and the

DO output

Within the input and output timing of the BR93LC66 the

drive from the µ-COM output to the DI input and a sig-

nal output from the DO output can be emitted at the

same time. This happens only for the 1 clock cycle (a

dummy bit “0” is output to the DO pin) which acquires

the AO address data during a read cycle. When the

address data AO = 1, the µ-COM output becomes a

direct current source for the DO pin.

The resistor R is the only resistance which limits this

current. Therefore, a resistor with a value which satis-

fies the µ-COM and the BR93LC66 current capacity is

required. When using a single control line, when a

dummy bit “0” is output to the DO, the µ-COM I / O

address data AO is also output. Therefore, the dummy

bit cannot be detected.

2) Feedback to the DI input from the DO output

Data is output from the DO pin and then feeds back

into the DI input through the resistor R. This happens

when:

• DO data is output during a read operation

• A READY / BUSY signal is output during WRITE or

WRAL operation

Such feedback does not cause problems in the basic

operation of the BR93LC66.

The µ-COM input level must be adequately maintained

for the voltage drop at R which is caused by the total

input leakage current for the µ-COM and the BR93LC-

66.

In the state in which SK is input, when the READY /

BUSY function is used, make sure that CS is dropped

to LOW within four clock pulses of the output of the

READY signal HIGH and the standby mode is restored.

For input after the fifth clock pulse, the READY HIGH

will be taken as the start bit and WDS or some other

mode will be activated, depending on the DI state.

11

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