HM5264165F-75 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM5264165F-75

64M LVTTL interface SDRAM 133 MHz/100 MHz

Hitachi -> Renesas Electronics 

HM5264165F/HM5264805F/HM5264405F-75/A60/B60

DQM Truth Table (HM5264165F)

Command

Upper byte write enable/output enable

Lower byte write enable/output enable

Upper byte write inhibit/output disable

Lower byte write inhibit/output disable

Note:

H: VIH. L: VIL. ×: VIH or VIL.

Write: IDID is needed.

Read: IDOD is needed.

Symbol

ENBU

ENBL

MASKU

MASKL

DQM Truth Table (HM5264805F/HM5264405F)

Command

Write enable/output enable

Write inhibit/output disable

Note:

H: VIH. L: VIL. ×: VIH or VIL.

Write: IDID is needed.

Read: IDOD is needed.

Symbol

ENB

MASK

CKE

n-1

n

H

×

H

×

H

×

H

×

DQMU

L

×

H

×

DQML

×

L

×

H

CKE

n-1

n

H

×

H

×

DQM

L

H

The SDRAM can mask input/output data by means of DQM, DQMU/DQML.

DQMU masks the upper byte and DQML masks the lower byte. (HM5264165F)

During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data

output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z,

disabling data output.

During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set

to High, the previous data is held (the new data is not written). Desired data can be masked during burst read

or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the

SDRAM operating instructions.

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