HM5117400BLS-8 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
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HM5117400BLS-8 Datasheet PDF : 25 Pages
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HM5117400B Series
Fast Page Mode Read-Modify-Write Cycle
HM5117400B
-6
-7
Parameter
Symbol Min Max Min Max
Fast page mode read-modify-write tPRWC
cycle time
85 —
96 —
delay time from
precharge tCPW
60 —
68 —
-8
Min Max
105 —
75 —
Unit Notes
ns
ns 14
Test Mode Cycle*19
Parameter
Test mode
Test mode
setup time
hold time
HM5117400B
-6
-7
Symbol Min Max Min
tWTS
0
—
0
tWTH
10 —
10
Max
—
—
-8
Min Max
0
—
10 —
Unit Notes
ns
ns
Refresh
Parameter
Symbol
Max
Unit
Note
Refresh period
t REF
32
ms
2048 cycles
Refresh period (L-version)
t REF
128
ms
2048 cycles
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing -only refresh or -before- refresh). If the
internal refresh counter is used, a minimum of eight -before- refresh cycles are required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
10
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