HIP0051 Просмотр технического описания (PDF) - Intersil
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HIP0051 Datasheet PDF : 5 Pages
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HIP0051
Pin Descriptions
VCC - Logic Power Supply
The VCC pin is the positive 5V logic voltage supply input for
the IC. The normal operating voltage range is 4.5 to 5.5V.
When switched on, the POR forces all outputs off.
SCK - Serial Clock
SCK is the clock input for the SPI interface. Output ON/OFF
control data is clocked into an eight stage shift register on
the rising edge of an external clock. This input has a Schmitt
trigger.
SI - Serial Data In
SI is the Serial Data Input pin for the SPI interface. The eight
Power Outputs are controlled by the serial data via the
Output Data Buffer. This input has a Schmitt trigger.
STR - Strobe for the SPI Interface
When the STR pin is high, data from the 8-bit shift register is
passed into the Output Data Buffers where it controls the
ON-OFF state of each output driver. The data is latched in
the Output Data Buffers on the trailing edge of the STR
pulse. This input has a Schmitt trigger.
SO - Serial Data Out
The Serial Data Out allows other ICs to be serially
cascaded. For example, a 10-bit LED driver may be located
behind the HIP0051. A controlling microprocessor may then
clock out 18 bits of information and simultaneously strobe
both parts. The cascaded ICs may be the same or different
from the HIP0051.
DR0 to DR7 - Outputs 0 Thru 7
The Drain Output pins of the DMOS Power Drivers are
capable of sinking 250mA.
EN - Enable
The Enable pin is an active low enable function for all eight
output drivers. When EN is high, drive from the Output Data
Buffer is held low and all output drivers are disabled. When
EN is low, the output drivers are enabled and data in the
8-bit shift register is transparent to the Output Data Buffer.
This input has a Schmitt trigger.
LGND and GND - Ground
LGND is the logic input power supply ground pin. The GND
pins are common grounds for the Power Output Drivers. The
power supplies for the logic and power circuits require a
common ground. To minimize ground bounce at the logic
input, the external ground return path for the GND pin should
be separate from the LGND pin. LGND and GND have com-
mon substrate ground connections on the chip.
OUTPUT CONTROL TABLE
STROBE
8-BIT SERIAL DATA (LATCHED)
OUTPUT
D1 D2 D3 D4 D5 D6 D7 D8 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8
0
0
0
0
0
0
0
0 OFF OFF OFF OFF OFF OFF OFF OFF
1
0
0
0
0
0
0
0 ON OFF OFF OFF OFF OFF OFF OFF
1
1
0
0
0
0
0
0 ON ON OFF OFF OFF OFF OFF OFF
1
1
1
0
0
0
0
0 ON ON ON OFF OFF OFF OFF OFF
1
1
1
1
0
0
0
0 ON ON ON ON OFF OFF OFF OFF
0
0
0
0
1
1
1
1 OFF OFF OFF OFF ON ON ON ON
1
1
1
1
1
1
1
1 ON ON ON ON ON ON ON ON
4
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