HFA3824A Просмотр технического описания (PDF) - Intersil
Номер в каталоге
Компоненты Описание
Список матч
HFA3824A Datasheet PDF : 40 Pages
| |||
HFA3824A
TABLE 5. TEST MODES (CONTINUED)
MODE DESCRIPTION TEST_CLK
TEST (7:0)
7 Bit Sync Test
Mode 2
LoadSQ
SQ (14:7) Bit Sync Ref-
Data
8 A/D Cal Test
Mode
A/D
CAL_CK
CRS, ED, “0”, ADCal
(4:0)
9 Reserved
10 Reserved
(0Ah)
11 Reserved
12 Reserved
13 Reserved
14 Correlator Test RXCLK
Mode 2
MAG (7:0)
15 Reserved
Definitions
Normal - Device in the full protocol mode (Mode 3).
TXCLK - Transmit clock (PN rate).
Initial Detect - Indicates that Signal Quality 1 and 2 (SQ1
and SQ2) exceed their programmed thresholds. Signal qual-
ities are a function of phase error and correlator magnitude
outputs.
ED - energy detect indicates that the RSSI value exceeds its
programmed threshold.
CRS - indicates that a signal has been acquired (PN
acquisition).
Mag - Magnitude output from the correlator.
DCLK - Data symbol clock.
FrqReg - Contents of the NCO frequency register.
Phase - phase of signal after carrier loop correction.
NCO PhaseAccumReg - Contents of the NCO phase
accumulation register.
LoadSQ - Strobe that samples and updates Signal Quality,
SQ1 and SQ2 values.
SQ2 - Signal Quality measure #2. Signal phase variance
after removal of data, 8 MSBs of most recent 16-bit stored
value.
RXCLK - Receive clock (RX sample clock). Nominally 22MHz.
BitSyncAccum - Real time monitor of the bit
synchronization accumulator contents, mantissa only.
SQ1 - Signal Quality measure #1. Contents of the bit sync
accumulator 8 MSBs of most recent 16-bit stored value.
A/D_Cal_ck - Clock for applying A/D calibration corrections.
ADCal - 5-bit value that drives the D/A adjusting the A/D
reference.
External AGC Control
The ADC cal output (pin 26) is a binary signal that fluctuates
between logic levels as the signals in the I and Q channels
are either at full scale or not. If the input level is too high, this
output will have a higher duty cycle, and visa versa. Thus,
this signal could be integrated with an R-C filter to develop
an AGC control voltage. The AGC feedback should be
designed to drive it to 50% duty cycle. In the case that an
external AGC is in use then the ADC calibration circuit must
not be programmed for automatic level adjustment.
Power Down Modes
The power consumption modes of the HFA3824A are
controlled by the following control signals.
Receiver Power Enable (RX_PE, pin 33), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 2), which disables the
transmitter when inactive.
Reset (RESET, pin 28), which puts the receiver in a sleep
mode when it is asserted at least 2 MCLKs after RX_PE is
set at its inactive state. The power down mode where, both
RESET and RX_PE are used is the lowest possible power
consumption mode for the receiver. Exiting this mode
requires a maximum of 10µs before the device is back at its
operational mode.
The contents of the Configuration Registers is not effected
by any of the power down modes. No reconfiguration is
required when returning to operational modes.
Table 6 describes the power down modes available for the
HFA3824A (VCC = 3.5V). The table values assume that all
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted and the RSSI Converter is disabled.
RX_PE
Inactive
TX_PE
Inactive
RESET
Active
Inactive
Inactive
Inactive
Inactive
Active
Inactive
Active
Inactive
Inactive
ICC Standby
TABLE 6. POWER DOWN MODES
22MHz
44MHz
DEVICE STATE
22mA
44mA
Both transmit and receive functions disabled. Device in sleep mode.
Control Interface is still active. Register values are maintained. Device
will return to its active state within 10µs.
30mA
48mA
Both transmit and receive operations disabled. Device will become in its
active state within 1µs.
32mA
50mA
Receiver operations disabled. Receiver will return in its active state with-
in 1µs.
32mA
50mA
Transmitter operations disabled. Transmitter will return to its active state
within 2 MCLKs.
300µA
All inputs at VCC or GND.
2-111
Share Link: 