HEF4516BF Просмотр технического описания (PDF) - Philips Electronics

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HEF4516BF

Binary up/down counter

Philips Electronics 

Philips Semiconductors

Binary up/down counter

Product specification

HEF4516B

MSI

DESCRIPTION

The HEF4516B is an edge-triggered synchronous

up/down 4-bit binary counter with a clock input (CP), an

up/down count control input (UP/DN), an active LOW

count enable input (CE), an asynchronous active HIGH

parallel load input (PL), four parallel inputs (P0 to P3), four

parallel outputs (O0 to O3), an active LOW terminal count

output (TC), and an overriding asynchronous master reset

input (MR).

Information on P0 to P3 is loaded into the counter while PL

is HIGH, independent of all other input conditions except

MR which must be LOW. When PL and CE are LOW, the

counter changes on the LOW to HIGH transition of CP.

Input UP/DN determines the direction of the count, HIGH

for counting up, LOW for counting down. When counting

up, TC is LOW when O0 and O3 are HIGH and CE is LOW.

When counting down, TC is LOW when O0 to O3 and

CE are LOW. A HIGH on MR resets the counter (O0 to

O3 = LOW) independent of all other input conditions.

Fig.2 Pinning diagram.

Fig.1 Functional diagram.

HEF4516BP(N): 16-lead DIL; plastic (SOT38-1)

HEF4516BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)

HEF4516BT(D): 16-lead SO; plastic (SOT109-1)

( ): Package Designator North America

PINNING

PL

P0 to P3

CE

CP

UP/DN

MR

TC

O0 to O3

parallel load input (active HIGH)

parallel inputs

count enable input (active LOW)

clock pulse input (LOW to HIGH,

edge triggered)

up/down count control input

master reset input

terminal count output (active LOW)

parallel outputs

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

2

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