HD74LS74AFPEL Просмотр технического описания (PDF) - Renesas Electronics

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HD74LS74AFPEL

Dual J-K Flip-Flops(with Preset/ Common Clear/ and Common Clock)

Renesas Electronics 

HD74LS74A

Testing Method

Test Circuit

1. ƒmax, tPLH, tPHL (Clock→Q, Q)

Input

P.G.

Zout = 50Ω

Input

P.G.

Zout = 50Ω

4.5V VCC Output Q

PR

D

Q

CK

CLR

Output Q

Q

Load circuit 1

RL

CL

Same as Load Circuit 1.

Notes:

1. Test is put into the each flip-flop.

2. CL includes probe and jig capacitance.

3. All diodes are 1S2074(H).

2. tPHL, tPLH (Clear or Preset→ Q, Q)

Input

P.G.

Zout = 50Ω

Input

P.G.

Zout = 50Ω

VCC Output Q

PR

D

Q

CK

CLR

Output Q

Q

Load circuit 1

RL

CL

Same as Load Circuit 1.

Notes:

1. Test is put into the each flip-flop.

2. CL includes probe and jig capacitance.

3. All diodes are 1S2074(H).

Rev.3.00, Jul.22.2005, page 4 of 7

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