HD74LS165AFPEL Просмотр технического описания (PDF) - Renesas Electronics

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HD74LS165AFPEL

Parallel-Load 8-bit Shift Register

Renesas Electronics 

HD74LS165A

Testing Method

Test Circuit

4.5V

VCC

P.G.

Zout = 50Ω

Input

Serial Input

Shift/Load

A

B

QH

C

D

E

F

G

QH

H

Clock

Clock

Inhibit

Output

Load circuit 1

RL

CL

Same as Load Circuit 1.

Notes: 1. CL includes probe and jig capacitance.

2. All diodes are 1S2074(H).

Waveforms 1

3V

Shift/

1.3V

Load

0V

tsu

3V

Serial

Input

1.3V

1.3V

0V

Notes:

tsu

tsu

3V

Clock

Inhibit

1.3V

1.3V

0V

A. The eight data inputs and the clock-inhibit input are low. Results are monitored at output QH at

Tn + 7.

B. The input pulse generators have the following characteristics: PRR < 1 MHz,

duty cycle < 50%, Zout ≈ 50 Ω, tTLH ≤ 15 ns, tTHL ≤ 6 ns.

Rev.3.00, Jul.15.2005, page 4 of 7

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