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HD6433044F

Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Renesas Electronics 

Item

Page

5.5.4 Usage Notes on 120

External Interrupts

Figure 5.9 IRQnF

Flag When Interrupt

Processing Is Not

Conducted

Revision (See Manual for Details)

Figure amended

IRQaF

IRQbF

Read Write

10

Read Write

1

0

10.2.3 Timer Mode 335

Register (TMDR)

Bit 6—Phase Counting

Mode Flag (MDF)

13.2.8 Bit Rate

Register (BRR)

473,

475

Table 13.3 Examples

of Bit Rates and BRR

Settings in

Asynchronous Mode

13.3.2 Operation in 492

Asynchronous Mode

Figure 13.8 Example

of SCI Receive

Operation (8-Bit Data

with Parity and One

Stop Bit)

Read Write IRQb

11

Execution

Occurrence condition 1

Read Write

0

0

Clear in error

Occurrence condition 2

Table amended

Counting Direction Down-Counting

Up-Counting

TCLKA pin

TCLKB pin

↑

High ↓

Low ↑

Low ↓

High

Low ↑

High ↓

High ↑

Low ↓

Table amended

φ (MHz)

3

3.6864

25

Bit Rate

(bits/s) n N

Error

(%)

nN

Error

(%)

nN

Error

(%)

110

1 212 0.03 2 64 0.70 3 110 –0.02

150

1 155 0.16 1 191 0.00 3 80 0.47

300

1 77 0.16 1 95 0.00 2 162 –0.15

600

0 155 0.16 0 191 0.00 2 80 0.47

1200

0 77 0.16 0 95 0.00 1 162 –0.15

2400

0 38 0.16 0 47 0.00 1 80 0.47

4800

0 19 –2.34 0 23 0.00 0 162 –0.15

9600

0 9 –2.34 0 11 0.00 0 80 0.47

19200

0 4 –2.34 0 5 0.00 0 40 –0.76

31250

0 2 0.00 0 3 –7.84 0 24 0.00

38400

0 1 22.07 0 2 0.00 0 19 1.73

Figure amended

Start

1

bit

Data

Parity Stop Start

bit bit bit

Parity Stop

Data

bit bit

1

0 D0 D1

D7 0/1 1

0 D0 D1

D7 0/1 1

Idle (mark)

state

RDRF

FER

1 frame

RXI

request

RXI interrupt handler

reads data in RDR and

clears RDRF flag to 0

Framing error,

ERI request

Rev. 3.00 Sep 27, 2006 page x of xxvi

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