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HD6433022F

16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Renesas Electronics 

Item

11.2.8 Bit Rate

Register (BRR)

Page

350

Table 11.3 Examples 352

of Bit Rates and BRR

Settings in

Asynchronous Mode

11.3.4 Synchronous 382

Operation

Figure 11.17 Example

of SCI Transmit

Operation

15.8.3 Error

485

Protection

Figure 15.13 Flash

Memory State

Transitions (Modes 5,

6, and 7 (on-chip ROM

enabled), high level

applied to FWE pin)

16.2.1 Connecting a 504

Crystal Resonator

Table 16.2 Crystal

Resonator Parameters

Revision (See Manual for Details)

Description amended

The CPU can always read and write BRR. BRR is initialized to

H'FF by a reset and in standby mode.

The baud rate generator is controlled separately for the

individual channels, so different values may be set for each.

Table 11.3 shows examples of BRR settings in asynchronous

mode. Table 11.4 shows examples of BRR settings in

synchronous mode.

Table amended

Bit Rate

(bits/s) n

110

2

150

2

300

1

φ (MHz)

6

Error

N

(%)

n

106 –0.44

2

77 0.16

2

155 0.16

2

12

Error

N

(%)

212 0.03

155 0.16

77 0.16

Figure amended

Transmit

direction

Serial clock

Serial data

Bit 0 Bit 1

Bit 7 Bit 0 Bit 1

TDRE

TEND

TXI

request

TXI interrupt handler

writes data in TDR

and clears TDRE

flag to 0

TXI

request

Figure amended

1 frame

Bit 6 Bit 7

TEI

request

Error protection mode

(software standby)

RD VF PR ER INIT FLER= 1

Preliminary deleted

Rev.2.00 Mar. 22, 2007 Page ix of xxiv

REJ09B0352-0200

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